Micron Sells the Memory Shortage as Five-Year Contracts

Datacenter customers want about 50% more memory than Micron can commit, CEO Sanjay Mehrotra said. Those same buyers have already pledged $22 billion in deposits on five-year take-or-pay contracts.

The unmet orders are being written into deals with floor prices Micron says will hold margins above any past cycle, through the end of 2030.

Every Chip Micron Makes Already Has a Buyer

Mehrotra said it from a construction site near company headquarters in Boise, Idaho, in a televised interview with Jim Cramer on August 20. He has spent more than 40 years in chips and co-founded SanDisk. Memory, he argued, is no longer a bid-for-the-lowest-price part.

Today there is no AI without memory. AI systems need more memory. They need higher performance memory. They need lower power memory. So, the value of memory, that equation has totally changed.

Sanjay Mehrotra, Chairman, President and CEO, Micron, on Mad Money

He added that memory has to be designed next to the processors it will sit beside, earlier in the customer’s development cycle. Autonomous vehicles, robots, and AI-enabled phones and PCs will all want more bits, he said, which is why he calls memory “the strategic infrastructure of the AI era.”

The supply line still does not match that talk. “All our customers across our end markets will buy everything that we make,” Mehrotra said, and datacenter customers want roughly 50% more than Micron can commit. On the June 24 earnings call the company had counted 16 strategic customer agreements. He said more have been signed since then. “They have committed to taking the supply. So, this gives us assurance of demand.”

The interview was taped at the Boise build, part of a planned $250 billion U.S. manufacturing and research outlay. Each of the two planned fabs is about the size of 10 football fields. The first is due to produce wafers in mid-2027.

How the Five-Year Memory Contracts Work

The agreements are take-or-pay. A customer commits to set volumes over a multi-year term and pays for them whether the chips get used or not. Most run from calendar 2026 through the end of 2030. Automotive deals generally run three years. Micron frames them as Strategic Customer Agreements, or SCAs, covering datacenter, consumer, and auto buyers.

Fourteen of the first 16 carry about $100 billion of remaining revenue at the contractual minimum price, which is a floor, not a forecast. Management expects actual billings above that if volumes or mix run richer. The largest deals set a ceiling near second-quarter 2026 market prices for existing products and a floor through the term. Several smaller SCAs use fixed prices or no bands at all.

WHAT THE FIRST 16 AGREEMENTS LOCK IN

For the banded deals, Mehrotra said the floor “enables a very robust gross margin for Micron, well above our peak quarterly margins in any past cycle.” Newer products such as LPDDR6, DDR6, and later HBM versions can be priced at a premium to the existing parts. The deposits show buyers will fund the boom’s working capital to hold a place in line.

The quarter that produced those contracts was already a blowout. Micron posted revenue of $41.46 billion for the period ended May 28, against $23.86 billion in the prior quarter and $9.30 billion a year earlier. GAAP net income was $28.24 billion, or $24.67 a diluted share. Datacenter revenue exceeded $25 billion, an annualized run rate over $100 billion. Datacenter SSD revenue exceeded $5 billion and more than doubled sequentially. Operating cash flow was $25.39 billion. Mehrotra said the fourth-quarter outlook is stronger still.

A Third as Many Bits per Wafer

The 50% gap is not only a booking problem. High-bandwidth memory, the stacked DRAM that sits beside AI accelerators, burns far more silicon per bit than ordinary DDR. Jim Handy, general director at Objective Analysis, told Hot Chips 2026 that HBM delivers about a third as many gigabytes per wafer as standard DRAM, “and that’s causing all DRAM to go into shortage because they’re all made on the same product process lines.”

Raghu Sreeramaneni, a Micron fellow for HBM design architecture, put the system mismatch in plain numbers. Compute is scaling at roughly 3 times every two years, he said, while HBM bandwidth is more like 2 times every two years, so “the memory wall is still present, and in fact, it may be getting worse.” HBM4 also doubles banks per DRAM die, from 128 on HBM3E to 256, which is more parallelism and more area lost to through-silicon vias.

Micron’s HBM4 12-high stack holds 36GB, same as HBM3E 12-high, but it is specified at more than 2.8 TB/s per stack on a 2048-pin bus running above 11.0 Gbps, more than double the prior generation. The company said the 12-high HBM4 ramp is tracking twice as fast as HBM3E 12-high and that it had already shipped over $1 billion of HBM4 by the June call. Volume production of that 36GB 12-high part, designed for NVIDIA’s Vera Rubin platform, began in the first quarter of the calendar year.

Each extra HBM layer also thins the dies, raises heat in the cube, and multiplies the chance that one bad via scraps the whole stack. That is yield math, not a slogan, and it is why making more HBM does not free up commodity DRAM on a one-for-one basis.

WHY THE SHORTAGE KEEPS SPREADING

• Wafer math: HBM needs about three times the silicon per bit of standard DDR, so every AI stack pulled off the line is DRAM that never reaches a PC or a phone.
• Shared lines: HBM and conventional DRAM still run on the same process tools, so a mix shift toward stacks tightens every other product.
• Decade of no shells: Handy said makers had not added factories for over 10 years because bits per wafer had been enough, until AI demand forced new cleanrooms.
• Node slowdown: Mehrotra said each new memory node now delivers slower bit growth, so wafer starts have to rise just to stand still.

On the June call he also said NAND makers are redirecting cleanroom space toward DRAM, which then squeezes flash as well. The mix shift is the tax. Datacenter HBM is paid first. Everything else waits.

Signed Buyers Get Supply, Everyone Else Waits

The contracts do not create extra wafers. They assign the wafers that exist. Four very large customers and three medium ones sit at the front of Micron’s book, with smaller automotive names on shorter terms. In a shortage, that ranking is the product. A hyperscaler that posts a deposit and signs take-or-pay gets a committed stream of DRAM, including HBM where the deal allows it. A PC builder or a phone brand that did not sign shops the residual.

That split is already how the market is behaving. The loud argument around Micron is that these deals break the old boom-and-bust script. The sharper reading is narrower. Floors and non-cancellable volumes move fab risk onto buyers who already want 50% more than the company will promise. They do not retire the open market. Until coverage actually reaches half of revenue, most bits can still trade, and a slump in that remainder still hits the income statement.

Mehrotra told Cramer the company is now in the customer’s design cycle earlier, because memory has to match the processor. That sounds like partnership. It is also lock-in. Once a stack is qualified next to a GPU or an ASIC, swapping suppliers is a year-plus science project, which is why buyers will pay a floor “well above” old peak margins to keep the line moving.

The Boise Fabs Will Not Help Until Mid-2027

Micron is not standing still. The company has committed to two leading-edge fabs in Boise, co-located with its Idaho research work, and says those plants plus two New York fabs and a Virginia modernization are in line for up to $6.4 billion in CHIPS Act direct funding. Idaho plans call for more than 17,000 new jobs. DRAM output at the first Boise fab is scheduled to begin in 2027, matching Mehrotra’s mid-2027 wafer date from the interview. The New York site broke ground in January and arrives later.

FROM THE JUNE CALL TO THE FIRST BOISE WAFERS

1. June 24, 2026: Micron reports the record quarter and 16 SCAs, and says tightness lasts beyond calendar 2027.
2. August 20, 2026: Mehrotra says datacenter customers want about 50% more than Micron can commit, and that more SCAs have been signed.
3. Mid-2027: The first Boise fab is due to start producing wafers, still inside the contract window.
4. 2028: Industry supply is expected to improve only gradually, with no line of sight to a full catch-up.
5. End of 2030: The typical five-year SCA term expires.

Greenfield memory fabs are large, slow, and short of skilled trades, Mehrotra said, and they need permits and extra power. Process technology is getting harder at every node. HBM’s rising trade ratio against non-HBM DRAM adds another drag. “Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand,” he told investors. He also expects 2027 to be tighter than 2026.

Most Memory Still Sells Without a Floor

The first 16 deals cover about 20% of DRAM volume and a third of NAND over the term. That is the number that should travel with the $100 billion headline. When all planned SCAs are done, Micron wants half or more of revenue under contract, and about 40% of revenue at fixed prices or ceilings near today’s market. Until then, the majority of bits still clear in a market that can fall.

THE COVERAGE GAP IN PLAIN FIGURES

• Locked DRAM: About one-fifth of bits sit under the first 16 SCAs through 2030.
• Locked NAND: About one-third of bits sit under those same deals.
• Still on the open market: The rest of the book, which is most of it, still prices with the cycle.
• HBM4 already sold: Calendar 2026 HBM supply, including HBM4, was described as fully contracted.

That leftover book is where a classic memory crash still lives. It is also where phone, PC, and auto teams that missed the first signing wave will shop. The deposits do not move a wafer from 2028 to 2026. They decide who is first in line when the wafer exists.

Why New Fabs Cannot Close the Gap Fast

New cleanrooms take years, and HBM stacking gets physically harder as dies get thinner and hotter, so the extra 50% datacenter buyers want will not appear as a sudden wave of bits. Mehrotra listed long construction lead times, a shortage of workers with critical trade skills, permitting, and the need for more energy infrastructure. On top of that, each new DRAM and NAND node is slower to add bits than the last, and every new HBM generation consumes more wafer area relative to DDR. The first Boise output in mid-2027 lands two years into contracts that last until 2030, which is why buyers are paying now to reserve supply that the new shells will not yet have made.

Micron can point to 1-gamma DRAM and G9 NAND ramping toward the highest-volume nodes in its history, and to next nodes due in the second half of calendar 2027. Those are process gains on existing shells. They are not a second Boise. Handy’s point still stands: the industry went more than a decade without adding factories because bits per wafer had been enough, and that habit is what AI demand ran into.

The 50% ask and the $22 billion already posted are the same fact seen from two sides. Customers cannot get the extra memory, so they buy the right to what exists, at floors Micron says sit above any prior-cycle peak, while the uncovered majority of bits still faces the old market. The first Boise fab is due to produce wafers in mid-2027, two years into contracts that run to 2030.

Disclaimer: This article is news reporting and analysis for general information only. It is not investment advice, a recommendation to buy or sell Micron or any other security, or a forecast of memory prices or company earnings. Readers who are considering a securities decision should consult a licensed financial adviser who can review their own objectives and risk tolerance. Revenue, contract, and capacity figures here reflect company statements and related sources as of September 2, 2026, and those figures can change with later filings, new agreements, or shifts in supply.